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Powertech Technology Readies Panel-Level Packaging Line for Q2 2027 Ramp-up
Electronic Technology · Semiconductors · cnyes · 2026-08-26
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Powertech Technology (PTI) has completed its automated fan-out panel-level packaging line, targeting mass production by Q2 2027 to meet AI chip demand.
What Happened
Advanced Packaging Breakthrough: Powertech Technology (PTI) has announced the completion of its fully automated fan-out panel-level packaging (FOPLP) line. This technology addresses the low area utilization of traditional 12-inch wafers, significantly boosting production efficiency for large-scale chips.
Production and Yield Targets: Utilizing 515x510mm panels, PTI can currently produce 45 large chips per panel with yields exceeding 90%. The company aims to push yields above 98% within the next two years, with mass production scheduled to commence in the second quarter of 2027.
Technical Advantages: PTI has overcome challenges such as warpage and thermal expansion through proprietary micro-bump technology and automated optical inspection. The use of a fan-out interposer architecture allows for cost-effective integration of computing chips and high-bandwidth memory (HBM).
Market Outlook: As AI architecture shifts toward inference, the demand for integrated chip packaging is surging. PTI's proven track record and cost-efficient packaging solutions position it as a vital partner for global tech firms looking to scale their AI hardware capabilities.